`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/12 11:47:48
// Design Name: 
// Module Name: axi_wmst_bridge
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module axi_wmst_bridge #(
                        // Base address of targeted slave
                        parameter  C_M_TARGET_SLAVE_BASE_ADDR    = 32'h800000,
                        // Burst Length. Supports 1, 2, 4, 8, 16, 32, 64, 128, 256 burst lengths
                        parameter integer C_M_AXI_BURST_LEN    = 16,
                        // Width of Address Bus
                        parameter integer C_M_AXI_ADDR_WIDTH    = 32,
                        // Width of Data Bus
                        parameter integer C_M_AXI_DATA_WIDTH    = 64
//                        // Width of User Write Address Bus
//                        parameter integer C_M_AXI_AWUSER_WIDTH    = 1,
//                        // Width of User Write Data Bus
//                        parameter integer C_M_AXI_WUSER_WIDTH    = 1,
//                        // Width of User Response Bus
//                        parameter integer C_M_AXI_BUSER_WIDTH    = 1
                        )(
        input   wire    M_AXI_ACLK,
        input   wire    M_AXI_ARESETN,
        output  wire    [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
        output  wire    [7 : 0] M_AXI_AWLEN,
        output  wire    [2 : 0] M_AXI_AWSIZE,
        output  wire    [1 : 0] M_AXI_AWBURST,
        output  wire     M_AXI_AWLOCK,
        output  wire    [3 : 0] M_AXI_AWCACHE,
        output  wire    [2 : 0] M_AXI_AWPROT,
        output  wire    [3 : 0] M_AXI_AWQOS,
        //output  wire    [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
        output  wire    M_AXI_AWVALID,
        input   wire    M_AXI_AWREADY,
        output  wire    [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
        output  wire    [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
        output  wire    M_AXI_WLAST,
        //output  wire    [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
        output  wire    M_AXI_WVALID,
        input   wire    M_AXI_WREADY,
        input   wire    [1 : 0] M_AXI_BRESP,
        //input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
        input   wire    M_AXI_BVALID,
        output  wire    M_AXI_BREADY,
        //HY_AXI
        output  wire    HYM_AXI_ACLK,
        output  wire    HYM_AXI_ARESETN,
        input   wire    [C_M_AXI_ADDR_WIDTH-1 : 0]HYM_AXI_AWADDR,
        input   wire    [7 : 0]HYM_AXI_AWLEN,
        input   wire    [2 : 0]HYM_AXI_AWSIZE,
        input   wire    [1 : 0]HYM_AXI_AWBURST,
        input   wire    HYM_AXI_AWLOCK,
        input   wire    [3 : 0]HYM_AXI_AWCACHE,
        input   wire    [2 : 0]HYM_AXI_AWPROT,
        input   wire    [3 : 0]HYM_AXI_AWQOS,
        //input   wire    [C_M_AXI_AWUSER_WIDTH-1 : 0]HYM_AXI_AWUSER,
        input   wire    HYM_AXI_AWVALID,
        output  wire    HYM_AXI_AWREADY,
        input   wire    [C_M_AXI_DATA_WIDTH-1 : 0]HYM_AXI_WDATA,
        input   wire    [C_M_AXI_DATA_WIDTH/8-1 : 0]HYM_AXI_WSTRB,
        input   wire    HYM_AXI_WLAST,
        //input   wire    [C_M_AXI_WUSER_WIDTH-1 : 0]HYM_AXI_WUSER,
        input   wire    HYM_AXI_WVALID,
        output  wire    HYM_AXI_WREADY,
        output  wire    [1 : 0]HYM_AXI_BRESP,
        //output     wire    [C_M_AXI_BUSER_WIDTH-1 : 0]HYM_AXI_BUSER,
        output  wire    HYM_AXI_BVALID,
        input   wire    HYM_AXI_BREADY,
        //
        output  wire    [C_M_AXI_ADDR_WIDTH-1:0]HYM_SLAVE_BASE_ADDR
        
    );
assign HYM_AXI_ACLK = M_AXI_ACLK;
assign HYM_AXI_ARESETN = M_AXI_ARESETN;
assign M_AXI_AWADDR = HYM_AXI_AWADDR;
assign M_AXI_AWLEN = HYM_AXI_AWLEN;
assign M_AXI_AWSIZE = HYM_AXI_AWSIZE;
assign M_AXI_AWBURST = HYM_AXI_AWBURST;
assign M_AXI_AWLOCK = HYM_AXI_AWLOCK;
assign M_AXI_AWCACHE = HYM_AXI_AWCACHE;
assign M_AXI_AWPROT = HYM_AXI_AWPROT;
assign M_AXI_AWQOS = HYM_AXI_AWQOS;
//assign M_AXI_AWUSER = HYM_AXI_AWUSER;
assign M_AXI_AWVALID = HYM_AXI_AWVALID;
assign HYM_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_WDATA = HYM_AXI_WDATA;
assign M_AXI_WSTRB = HYM_AXI_WSTRB;
assign M_AXI_WLAST = HYM_AXI_WLAST;
//assign M_AXI_WUSER = HYM_AXI_WUSER;
assign M_AXI_WVALID = HYM_AXI_WVALID;
assign HYM_AXI_WREADY = M_AXI_WREADY;
assign HYM_AXI_BRESP = M_AXI_BRESP;
//assign HYM_AXI_BUSER = M_AXI_BUSER;
assign HYM_AXI_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = HYM_AXI_BREADY;
//
assign HYM_SLAVE_BASE_ADDR = C_M_TARGET_SLAVE_BASE_ADDR;
endmodule